The Memory Unit will contain all the addressable memory and devices that will be accessible to the LEO-1 CPU. It will be constructed on a single board which will be at the top of the stack. The current version, on perfboard, took months to build and is not quite finished, but the part that has been built works. Since the Register Unit and ALU came out so well on PCBs, I'm considering redoing this board on a PCB as well, and putting even more memory on it.
The design of the address decoder allows for 8 banks of ROM, 8 banks of RAM, a real-time clock, two 8-position DIP switches, 16 front panel switches and two 8255 peripheral controllers, one for general I/O and one for controlling an IDE hard drive. There is also a pair of ZIF sockets on the board for easy insertion and removal of ROMs while testing. These sockets can be mapped to any of the 8 ROM banks using a rotating DIP switch.
The 'ROM' is actually EEPROM but I'll use the phrase ROM when referring to it. The exact part I'm using is the Greenliant GLS29EE010 which is an inexpensive 128K byte Flash memory. Two of these side by side allows 128K (16-bit) words. The total addressable ROM size is therefore 1 megaword, however the board will only hold 3 pairs of ROM chips plus the ZIF sockets making a total of 512 kilowords.
The main memory chip I'm using is the Alliance AS6C4008 which is a 512K byte static RAM. Two of these side by side allows 512K (16-bit) words. The total addressable RAM size is therefore 4 megawords, however the board will only hold 7 pairs of RAM chips making a total of 3.5 megawords.
This picture shows the test board connected to the memory board and the memory displaying the contents of address zero from the high 8-bits of ROM, which is installed in the left-hand ZIF socket:
This picture shows the back of the memory board. You can see that at first I was trying to use regular 26 AWG wire but it soon became apparent that I was not going to succeed using wire with such thick insulation. I changed to 28 and 32 AWG 'magnet' wire and things got a lot easier.
This picture shows the state of the memory board as of New Year 2016. The I/O port sockets and headers are now fitted along with the front panel LEDs which are showing the contents of the Address and Data Buses.